The present invention relates to a cell multiplexer and particularly relates to a cell multiplexer having a "cell delineation" function in which: relatively low-bit-rate fixed-length packets (cells) of an asynchronous transfer mode (hereinafter referred to as "ATM") received from subscriber lines are stored in a buffer memory; and boundaries between cells are identified so that correct data blocks thus read are transmitted to an output line.
As a conventional cell multiplexer, there is known a structure having cell delineation circuits corresponding to respective lines for performing cell multiplexing after cell synchronization, for example, as disclosed in "Discussion of A Header Error Check Calculation Circuit" reported in the Institute of Electronics, Information and Communication Engineers, 1990 Spring National Conference, Japan.
According to the conventional structure, however, one cell delineation circuit can process a signal in only one input line, so that a plurality of cell delineation circuits are required correspondingly to respective input lines even in the case where the transmission bit rate in the lines is low. For example, in the case of a system in which input line signals transmitted at the bit rate of about 6.3 mega-bits per second are transmitted to the ATM switch side while 21 input lines are multiplexed, 21 cell delineation circuits are required. In addition, the conventional structure requires memories for storing cell signals correspondingly to respective lines for the purpose of cell multiplexing, so that the hardware size thereof becomes large.